Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array

The binary coded decimal (BCD) system is suitable for digital communication, which can be designed by field programmable gate array (FPGA) technology, where look up table (LUT) is one of the major components of FPGA. In this study, the authors proposed a low power and area efficient LUT-based BCD ad...

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Bibliographic Details
Published in:IET circuits, devices & systems devices & systems, 2016-05, Vol.10 (3), p.163-172
Main Authors: Sworna, Zarrin Tasnim, UlHaque, Mubin, Tara, Nazma, Hasan Babu, Hafiz Md, Biswas, Ashis Kumar
Format: Article
Language:English
Subjects:
2-input LUT
adders
Adding circuits
Algorithms
BCD addition
BCD digit
binary codes
Circuit design
Circuits
CMOS
Communication systems
compact BCD adder
controller circuit
Critical path
Decimals
Design
Devices
Electric potential
field programmable gate array
Field programmable gate arrays
FPGA
Integrated circuits
look up table
Lookup tables
low-power area efficient binary coded decimal adder
low-power electronics
memory cell
Power consumption
Power management
read operation
read-write voltage
table lookup
Transistors
write operation
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Summary:The binary coded decimal (BCD) system is suitable for digital communication, which can be designed by field programmable gate array (FPGA) technology, where look up table (LUT) is one of the major components of FPGA. In this study, the authors proposed a low power and area efficient LUT-based BCD adder which is constructed basically in three steps: First, a new technique is introduced for the BCD addition to obtain the correct BCD digit. Second, a new controller circuit of LUT is presented which is designed to select and send Read/Write voltage to memory cell for performing Read or Write operation. Finally, a compact BCD adder is designed using the proposed LUT. Their proposed 2-input LUT outperforms the existing best one providing 65.8% improvement in terms of area, 44.1% for Read operation and 43.5% for Write operation in power consumption. The proposed BCD adder using FPGA gains a radical achievement compared with the existing best-known LUT-based BCD adder providing prominent better performance of 65.6% in area and 48.3% less power consumption.
ISSN:1751-858X
1751-8598
1751-8598
DOI:10.1049/iet-cds.2015.0213