New Proposal for MCML Based Three-Input Logic Implementation

• Published in: VLSI Design 2016-01, Vol.2016, p.93-102
• Main Authors: Pandey, Neeta, Gupta, Kirti, Choudhary, Bharat
• Format: Article
• Language: English
• Subjects: CMOS; Communication; Design engineering; Field programmable gate arrays; Gates (circuits); Logic; Multiplexing; Parameters; Power supply; Proposals; Transistors; Values
• ISSN: 1065-514X; 1563-5171
• DOI: 10.1155/2016/8712768

This paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML) style. The conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. The new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR) gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is analyzed and SPICE simulations using TSMC 180 nm CMOS technology parameters are included to support the theoretical concept. The performance of the proposed circuit is compared with its counterparts based on CMOS complementary pass transistor logic, conventional MCML, and cascading of existing two input tripple-tail XOR cells and applying triple-tail concept in conventional MCML topology. It is found that the proposed XOR gate performs best in terms of most of the performance parameters. The sensitivity of the proposed XOR gate towards process variation shows a variation of 1.54 between the best and worst case. As an extension, a realization of 4 : 1 multiplexer has also been included.