Efficient bit-parallel subcircuit extraction using CUDA

Summary Wafer processing technology has been improving rapidly. Moore's law has been exceeded as the number of transistors in a dense integrated circuit, now increases threefold or more, approximately every year. The integrated circuit has gone from very large scale to giga large scale. The ext...

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Bibliographic Details
Published in:Concurrency and computation 2016-11, Vol.28 (16), p.4326-4338
Main Authors: Hung, Che-Lun, Lin, Chun-Yuan, Ou, Chia-Shin, Tseng, Yuan-Hong, Hung, Po-Yen, Li, Ship-Peng, Fu, Chun-Ting
Format: Article
Language:English
Subjects:
Algorithms
Computation
Concurrency
Extraction
GPU
Graphics processing units
integrated circuit
Integrated circuits
Semiconductor devices
subcircuit
Very large scale
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Summary:Summary Wafer processing technology has been improving rapidly. Moore's law has been exceeded as the number of transistors in a dense integrated circuit, now increases threefold or more, approximately every year. The integrated circuit has gone from very large scale to giga large scale. The extraction of subcircuits has therefore become computation‐intensive. In this paper, we propose an efficient bit‐parallel subcircuit extraction algorithm using graphic processing units. We conducted experimental trials and demonstrated that the proposed algorithm can achieve high throughput, suggesting practical applications in the extraction of subcircuits. Copyright © 2015 John Wiley & Sons, Ltd.
ISSN:1532-0626
1532-0634
DOI:10.1002/cpe.3732