Efficient ASIC and FPGA implementation of cube architecture

• Published in: Chronic diseases and translational medicine 2017-01, Vol.11 (1), p.43-49
• Main Authors: Barik, Ranjan Kumar, Pradhan, Manoranjan
• Format: Article
• Language: English
• Subjects: addition operation; Algorithms; application specific integrated circuits; Architecture; ASIC implementation; binary radix‐2 number system; cadence tool; Computer simulation; cube operation; Cubes; cubic architecture; decimal numbers; Design; digital platforms; Encounter(R) RTL Compiler RC13.10 v13.10‐s006_1; Field programmable gate arrays; FPGA implementation; generalised architecture; high‐speed application; hypercube networks; magnitude number; Mathematical analysis; Mathematical models; Mathematics; microprocessor environment; Multiplication & division; Number systems; performance parameters; Platforms; Research Article; Synthesis; synthesis reports; Vedic mathematics; Xilinx ISE 14.1 software; Yavadunam sutra
• ISSN: 1751-8601; 1751-861X; 2095-882X; 1751-861X; 2589-0514
• DOI: 10.1049/iet-cdt.2016.0043

This study presents a generalised architecture for cube operation based on Yavadunam sutra of Vedic mathematics. This algorithm converts the cube of a large magnitude number into smaller magnitude number and addition operation. The Vedic sutra for decimal numbers is extended to binary radix-2 number system considering digital platforms. The cubic architecture is synthesised and simulated using Xilinx ISE 14.1 software and implemented on various Field-programmable gate array devices for comparison purpose. The Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of cadence tool is also used considering Application specific integrated circuit platform. The performance parameters such as delay, area and power are obtained from synthesis reports. The results show that the proposed architecture is useful for less area and high-speed application in microprocessor environment.