The GBT-FPGA core: features and challenges

Initiated in 2009 to emulate the GBTX (Gigabit Transceiver) serial link and test the first GBTX prototypes, the GBT-FPGA project is now a full library, targeting FPGAs (Field Programmable Gate Array) from Altera and Xilinx, allowing the implementation of one or several GBT links of two different typ...

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Bibliographic Details
Published in:Journal of instrumentation 2015-03, Vol.10 (3), p.C03021-C03021
Main Authors: Marin, M. Barros, Baron, S., Feger, S.S., Leitao, P., Lupu, E.S., Soos, C., Vichoudis, P., Wyllie, K.
Format: Article
Language:English
Subjects:
Clocks
Field programmable gate arrays
Flavours
Instrumentation
Links
Serials
Transceivers
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Summary:Initiated in 2009 to emulate the GBTX (Gigabit Transceiver) serial link and test the first GBTX prototypes, the GBT-FPGA project is now a full library, targeting FPGAs (Field Programmable Gate Array) from Altera and Xilinx, allowing the implementation of one or several GBT links of two different types: "Standard" or "Latency-Optimized". The first major version of this IP Core was released in April 2014. This paper presents the various flavours of the GBT-FPGA kit and focuses on the challenge of providing a fixed and deterministic latency system both for clock and data recovery for all FPGA families.
ISSN:1748-0221
1748-0221
DOI:10.1088/1748-0221/10/03/C03021