Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2009-05, Vol.17 (5), p.674-687
• Main Authors: Leary, G., Srinivasan, K., Mehta, K., Chatha, K.S.
• Format: Article
• Language: English
• Subjects: Algorithm design and analysis; Algorithms; Applied sciences; Architecture; Design automation; Design engineering; Design. Technologies. Operation analysis. Testing; Electronics; Energy consumption; Exact sciences and technology; genetic algorithms; Genetics; Hardware; Input-output equipment; Integrated circuits; Interconnection; Multiprocessor interconnection networks; Network synthesis; Network topology; Network-on-a-chip; network-on-chip (NoC); Power consumption; Power generation; Power system interconnection; Routers; routing; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; System-on-a-chip; Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2008.2011205

The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection architecture that can support the communication requirements for the SoC with the desired performance. This paper presents a genetic algorithm-based automated design technique that synthesizes an application specific NoC topology and routes the communication traces on the interconnection network. The technique operates on the system-level floorplan of the system on chip (SoC) and accounts for the power consumption in the physical links and the routers. The design technique solves a multi-objective problem of minimizing the power consumption and the router resources. It generates a Pareto curve of the solution set, such that each point in the curve represents a tradeoff between power consumption and associated number of NoC routers. The performance and quality of solutions produced by the technique are evaluated by experimentation with benchmark applications and comparisons with existing approaches.