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Phase Synchronization Operator for On-Chip Brain Functional Connectivity Computation

This paper presents an integer-based digital processor for the calculation of phase synchronization between two neural signals. It is based on the measurement of time periods between two consecutive minima. The simplicity of the approach allows for the use of elementary digital blocks, such as regis...

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Bibliographic Details
Published in:IEEE transactions on biomedical circuits and systems 2019-10, Vol.13 (5), p.957-970
Main Authors: Delgado-Restituto, Manuel, Romaine, James Brian, Rodriguez-Vazquez, Angel
Format: Article
Language:English
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Summary:This paper presents an integer-based digital processor for the calculation of phase synchronization between two neural signals. It is based on the measurement of time periods between two consecutive minima. The simplicity of the approach allows for the use of elementary digital blocks, such as registers, counters, and adders. The processor, fabricated in a 0.18-μm CMOS process, only occupies 0.05 mm 2 and consumes 15 nW from a 0.5 V supply voltage at a signal input rate of 1024 S/s. These low-area and low-power features make the proposed processor a valuable computing element in closed-loop neural prosthesis for the treatment of neural disorders, such as epilepsy, or for assessing the patterns of correlated activity in neural assemblies through the evaluation of functional connectivity maps.
ISSN:1932-4545
1940-9990
DOI:10.1109/TBCAS.2019.2931799