Noise Prediction for Rate Multiplier and Binary Adder Frequency Synthesizers

The theory for design of a rate multiplier or a binary adder frequency synthesizer for a specified level of noise attenuation is developed. Examples are presented to demonstrate the design procedure and the pattern of the pulse train output. The phase jitter associated with each pulse is characteriz...

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Bibliographic Details
Published in:IEEE transactions on aerospace and electronic systems 1978-07, Vol.AES-14 (4), p.677-684
Main Authors: Wilcox, Alan D., Mcvey, Eugene S., White, Eward J.
Format: Article
Language:English
Subjects:
Attenuation
Computer simulation
Equations
Frequency synthesizers
Jitter
Noise level
Phase measurement
Phase modulation
Pulse measurements
Pulse modulation
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Description
Summary:The theory for design of a rate multiplier or a binary adder frequency synthesizer for a specified level of noise attenuation is developed. Examples are presented to demonstrate the design procedure and the pattern of the pulse train output. The phase jitter associated with each pulse is characterized and illustrated in the time domain. The maximum absolute phase deviation is used as a measure of the phase modulation amplitude of the pulse train. Computer simulation resulted in simple equations approximating the amplitude of worst case spectral components.
ISSN:0018-9251
1557-9603
DOI:10.1109/TAES.1978.308699