SOI/CMOS circuits fabricated in zone-melting-recrystallized Si films on SiO2-coated Si substrates

A CMOS test circuit chip containing six arrays of 360 to 533 parallel transistors, two 31-stage ring oscillators, and two inverter chains has been designed for evaluating SOI wafers prepared by using the graphite strip-heater technique for zone-melting recrystallization of poly-Si films on SiO 2 -co...

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Bibliographic Details
Published in:IEEE electron device letters 1982-12, Vol.3 (12), p.398-401
Main Authors: Tsaur, B.Y., Fan, J.C.C., Chapman, R.L., Geis, M.W., Silversmith, D.J., Mountain, R.W.
Format: Article
Language:English
Subjects:
Boron
Circuit testing
Implants
Integrated circuit testing
Inverters
MOSFETs
Ring oscillators
Semiconductor device measurement
Semiconductor films
Substrates
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Summary:A CMOS test circuit chip containing six arrays of 360 to 533 parallel transistors, two 31-stage ring oscillators, and two inverter chains has been designed for evaluating SOI wafers prepared by using the graphite strip-heater technique for zone-melting recrystallization of poly-Si films on SiO 2 -coated Si substrates. One 2-in-diameter wafer has been evaluated in detail by testing all the circuits on each of 98 chips fabricated in the recrystallized film. These measurements reveal a good yield of functional circuits, and most of the failures can be explained by obvious metallization defects. The operating characteristics of each type of circuit are quite uniform from chip to chip. For the ring oscillators, which have a 5 µm gate length and fan in and out of one, at a supply voltage of 5 V the switching delay time is about 2 n s per stage and the power-delay product is 0.2-0.3 pJ per stage.
ISSN:0741-3106
1558-0563
DOI:10.1109/EDL.1982.25613