A high-speed 8 x 8-bit CMOS parallel array processor

The authors present an architecture for an 8-b x 8-b real-time parallel array processor that can be used for high-speed digital signal processing applications. The processor generates 18-b outputs from a stream of 8-b input data and a set of 8-b predetermined coefficients. The processor has been des...

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Bibliographic Details
Published in:IEEE Southeastcon '92, 1992 1992, 1992-01, Vol.ol. 2, p.828
Main Authors: Lee, Kwang-Keun, Deshmukh, R G
Format: Article
Language:English
Online Access:Get full text
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Summary:The authors present an architecture for an 8-b x 8-b real-time parallel array processor that can be used for high-speed digital signal processing applications. The processor generates 18-b outputs from a stream of 8-b input data and a set of 8-b predetermined coefficients. The processor has been designed in 1.5- mu m CMOS technology, analyzed for its timing, and functionally simulated by a hardware description language and a schematic simulator. The processor includes a pipelined array of multiplier-accumulators which provides parallel operation to the processor. The processor does not use parallel operation for an input rate lower than 28.5 Msamples/s, but the degree of parallelism was increased up to three for an input rate higher than 57.0 Msamples/s. This increase of the degree of parallelism resulted in a maximum throughput of 60.2 Msamples/s.