A gallium arsenide SDFL gate array with on-chip RAM

• Published in: IEEE transactions on electron devices 1984-01, Vol.31 (2), p.144-156
• Main Authors: Vu, T.T., Roberts, P.C.T., Nelson, R.D., Lee, G.M., Hanzal, B.R., Lee, K.W., Zafar, N., Lamb, D.R., Helix, M.J., Jamison, S.A., Hanka, S.A., Brown, J.C., Shur, M.S.
• Format: Article
• Language: English
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/T-ED.1984.21492

A GaAs gate array has been fabricated featuring 432 SDFL cells, 32 interface I/O buffer cells, and four 4 × 4 bit static RAM's. Each Schottky diode field-effect transistor logic (SDFL) cell can be programmed with 3 options as an unbuffered or buffered NOR gate, or as a dual OR/NAND gate. The interface I/O cell can be programmed for ECL, TTL, CMOS, and SDFL logic families. Each 16 bit RAM is fully decoded using depletion mode MESFET's with SDFL circuit approach. The chip size is 147 mils × 185 mils, and the total power dissipation of the whole chip is less than 3 W. Testing of the cell array has given yields of 70 percent for the 101-stage ring oscillators and about 90 percent for the I/O buffers, memory cells, and 25-stage ring oscillators in a wafer. The best speed performance of the unbuffered SDFL gate is 150 ps for fan-out and fan-in of 1 and the load of 100 µm of interconnect. The average power of the SDFL gate is 1.5 mW. The results demonstrated the feasibility of the GaAs SDFL for fast gate array and memory applications.