The architecture of SM3 - A dynamically partionable multicomputer system

• Published in: IEEE transactions on computers 1986-09, Vol.C-35, p.790-802
• Main Authors: Baru, C K, Su, S Y W
• Format: Article
• Language: English
• ISSN: 0018-9340

The architecture of a multicomputer system with switchable main memory modules (SM3) is presented. This architecture supports the efficient execution of parallel algorithms for nonnumeric processing by: (1) allowing the share of switchable main memory modules between computers, (2) supporting dynamic partitioning of the system, and (3) employing global control lines to efficiently support interprocessor communication. Data transfer time is reduced to memory switching time by allowing some main memory modules to be switched between processors. Dynamic partitioning gives a common bus system the capability of an MIMD machine while performing global operations. The global control lines establish a quick and efficient high-level protocol in the system. The network is supervised by a control computer which oversees network partitioning and other global functions. The hardware involved is quite simple and the network is easily extensible. A simulation study using discrete event simulation techniques has been carried out and the results of the study are presented. The architecture of this system is compared to those of conventional local area networks and shared-memory systems in order to establish the distinct nature and characteristics of a multicomputer system based on the SM3 concept. (Author)