A dual-port FASTBUS memory to test the L3 data acquisition system

A dual-port 0.25-Mbytes (64 K*32 bits) FASTBUS memory module is described which implements a large set of functions on the Crate Port, while the Cable Port is mainly used for data transfers. Both linear and circular FIFO-like modes are software-selectable. Two pointers are available for write and re...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 1988-04, Vol.35 (2), p.1006-1010
Main Authors: Cristofori, P.P., Cesaroni, F., Falciano, S., Medici, G.
Format: Article
Language:English
Subjects:
Buffer storage
Communication cables
computer applications
Control systems
Costs
Data acquisition
data collection
Detectors
Fastbus
high energy physics
information systems
Memory architecture
nuclear energy
physics
Superluminescent diodes
System testing
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Description
Summary:A dual-port 0.25-Mbytes (64 K*32 bits) FASTBUS memory module is described which implements a large set of functions on the Crate Port, while the Cable Port is mainly used for data transfers. Both linear and circular FIFO-like modes are software-selectable. Two pointers are available for write and read operations, respectively. The memory, successfully used to test the L3 event builders, exhibits features of an interesting, general purpose, FASTBUS module for event buffering in large data acquisition systems.< >
ISSN:0018-9499
1558-1578
DOI:10.1109/23.3691