Electron beam lithography of sub-0.1μm circuits

This paper describes the high resolution electron beam system and the lithography processes developed for the fabrication of ultra high speed, sub-0.1μm silicon FET circuits and other projects where complex multi-level structures with highly accurate overlay are required. Noise sources and short ter...

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Bibliographic Details
Published in:Microelectronic engineering 1989, Vol.9 (1), p.183-186
Main Authors: Rishton, S.A., Kern, D.P., Kratschmer, E., Chang, T.H.P.
Format: Article
Language:English
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Summary:This paper describes the high resolution electron beam system and the lithography processes developed for the fabrication of ultra high speed, sub-0.1μm silicon FET circuits and other projects where complex multi-level structures with highly accurate overlay are required. Noise sources and short term instability in the lithography tool have been reduced to less than 4nm peak-to-peak, while still accepting 125mm wafers. Devices and circuits have been fabricated with 70nm polysilicon gates and level-to-level overlay of typically 30nm over a 250μm field. The devices have yielded record transconductance results of more than 910mS/mm at 77 K, and have shown clear evidence of velocity overshoot. Device switching speeds of 13 picoseconds have been observed in ring oscillator circuits.
ISSN:0167-9317
1873-5568
DOI:10.1016/0167-9317(89)90043-9