Laser simulation of single-event upset in a p-well CMOS counter

A laser illumination method was used to simulate single-event upset (SEU) in a p-well complementary metal-oxide-semiconductor (CMOS) logic circuit. It was found that, unlike the case of the static random access memory (RAM), the sensitivity of a logic circuit to SEU is not necessarily linearly depen...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 1989-02, Vol.36 (1), p.1330-1332
Main Authors: Mazer, J.A., Kang, K., Buchner, S.
Format: Article
Language:English
Subjects:
Applied sciences
Circuit simulation
CMOS logic circuits
CMOS memory circuits
Counting circuits
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuits
Lighting
Logic circuits
Read-write memory
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Single event upset
SRAM chips
Voltage
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Summary:A laser illumination method was used to simulate single-event upset (SEU) in a p-well complementary metal-oxide-semiconductor (CMOS) logic circuit. It was found that, unlike the case of the static random access memory (RAM), the sensitivity of a logic circuit to SEU is not necessarily linearly dependent on the supply voltage and that its maximum hardness is achieved at the lower end of the voltage operating range. It is concluded that even though its greatest potential lies in the area of wafer-level hardness assurance the pulsed laser technique can also be used to assess changes in circuit design that have been implemented to increase SEU hardness.< >
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.1989.574133