Contrasting instruction-fetch time and instruction-decode time branch prediction mechanisms: Achieving synergy through their cooperative operation

We present a new design in which two branch prediction mechanisms are used in conjunction. We show that the combination of these mechanisms will reduce branch penalty, while also reducing chip area.

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Bibliographic Details
Published in:Microprocessing and microprogramming 1992, Vol.35 (1), p.401-408
Main Authors: Kaeli, David R., Emma, Philip G., Knight, Joshua W., Puzak, Thomas R.
Format: Article
Language:English
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Description
Summary:We present a new design in which two branch prediction mechanisms are used in conjunction. We show that the combination of these mechanisms will reduce branch penalty, while also reducing chip area.
ISSN:0165-6074
DOI:10.1016/0165-6074(92)90346-9