Choice of power-supply voltage for half-micrometer and lower submicrometer CMOS devices

The tradeoff between circuit performance and reliability is theoretically and experimentally examined in detail, down to half-micrometer and lower submicrometer gate lengths, taking into account high-field effects on MOSFETs. Some guidelines for optimum power-supply voltage and process/device parame...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on electron devices 1990-05, Vol.37 (5), p.1334-1342
Main Authors: Kakumu, M., Kinugawa, M., Hashimoto, K.
Format: Article
Language:English
Subjects:
Circuit optimization
CMOS process
Guidelines
Length measurement
Maintenance
MOS devices
MOSFETs
Reliability theory
Thickness measurement
Voltage
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The tradeoff between circuit performance and reliability is theoretically and experimentally examined in detail, down to half-micrometer and lower submicrometer gate lengths, taking into account high-field effects on MOSFETs. Some guidelines for optimum power-supply voltage and process/device parameters for half-micrometer and lower submicrometer CMOS devices are proposed in order to maintain MOS device reliability and achieve high circuit performance. It is shown that power-supply voltage must be reduced to maintain reliability and improved performance and that the optimum voltage reduction follows the square root of the design rule. Trends for scaling down power-supply voltage have been experimentally verified by results obtained from measurements on CMOS devices over a wide range of gate oxide thickness (7-45 nm) and gate lengths (0.3-2.0 mu m).< >
ISSN:0018-9383
1557-9646
DOI:10.1109/16.108196