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Layer assignment for printed circuit boards and integrated circuits
The layer assignment problem arises in printed circuit board (PCB) and integrated circuit (IC) design. It involves the assignment of interconnect wiring to various planes of a PCB or to various layers of interconnect wires in an IC. This paper reviews basic techniques for layer assignment in both PC...
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Published in: | Proceedings of the IEEE 1992-02, Vol.80 (2), p.311-331 |
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Language: | English |
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cited_by | cdi_FETCH-LOGICAL-c275t-7681df02f08654804691b77221e51fa6174bebd37b62660af0071b1c173cca463 |
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cites | cdi_FETCH-LOGICAL-c275t-7681df02f08654804691b77221e51fa6174bebd37b62660af0071b1c173cca463 |
container_end_page | 331 |
container_issue | 2 |
container_start_page | 311 |
container_title | Proceedings of the IEEE |
container_volume | 80 |
creator | Joy, D.A. Ciesielski, M.J. |
description | The layer assignment problem arises in printed circuit board (PCB) and integrated circuit (IC) design. It involves the assignment of interconnect wiring to various planes of a PCB or to various layers of interconnect wires in an IC. This paper reviews basic techniques for layer assignment in both PCBs and ICs. Two types of layer assignment are considered: (1) constrained layer assignment in which routing of interconnections is given and the objective is to assign wires to specific layers, and (2) unconstrained, or topological, layer assignment, in which both the physical routing of interconnections and assignment of the wires to layers is sought. Various objective functions, such as via minimization and minimization of signal delays through interconnect lines are discussed.< > |
doi_str_mv | 10.1109/5.123300 |
format | article |
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Various objective functions, such as via minimization and minimization of signal delays through interconnect lines are discussed.< ></description><identifier>ISSN: 0018-9219</identifier><identifier>EISSN: 1558-2256</identifier><identifier>DOI: 10.1109/5.123300</identifier><identifier>CODEN: IEEPAD</identifier><language>eng</language><publisher>IEEE</publisher><subject>Etching ; Insulation ; Integrated circuit interconnections ; Manufacturing ; Minimization ; Printed circuits ; Routing ; Very large scale integration ; Wires ; Wiring</subject><ispartof>Proceedings of the IEEE, 1992-02, Vol.80 (2), p.311-331</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c275t-7681df02f08654804691b77221e51fa6174bebd37b62660af0071b1c173cca463</citedby><cites>FETCH-LOGICAL-c275t-7681df02f08654804691b77221e51fa6174bebd37b62660af0071b1c173cca463</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/123300$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,27905,27906,54777</link.rule.ids></links><search><creatorcontrib>Joy, D.A.</creatorcontrib><creatorcontrib>Ciesielski, M.J.</creatorcontrib><title>Layer assignment for printed circuit boards and integrated circuits</title><title>Proceedings of the IEEE</title><addtitle>JPROC</addtitle><description>The layer assignment problem arises in printed circuit board (PCB) and integrated circuit (IC) design. It involves the assignment of interconnect wiring to various planes of a PCB or to various layers of interconnect wires in an IC. This paper reviews basic techniques for layer assignment in both PCBs and ICs. Two types of layer assignment are considered: (1) constrained layer assignment in which routing of interconnections is given and the objective is to assign wires to specific layers, and (2) unconstrained, or topological, layer assignment, in which both the physical routing of interconnections and assignment of the wires to layers is sought. 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It involves the assignment of interconnect wiring to various planes of a PCB or to various layers of interconnect wires in an IC. This paper reviews basic techniques for layer assignment in both PCBs and ICs. Two types of layer assignment are considered: (1) constrained layer assignment in which routing of interconnections is given and the objective is to assign wires to specific layers, and (2) unconstrained, or topological, layer assignment, in which both the physical routing of interconnections and assignment of the wires to layers is sought. Various objective functions, such as via minimization and minimization of signal delays through interconnect lines are discussed.< ></abstract><pub>IEEE</pub><doi>10.1109/5.123300</doi><tpages>21</tpages></addata></record> |
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identifier | ISSN: 0018-9219 |
ispartof | Proceedings of the IEEE, 1992-02, Vol.80 (2), p.311-331 |
issn | 0018-9219 1558-2256 |
language | eng |
recordid | cdi_proquest_miscellaneous_25699393 |
source | IEEE Xplore (Online service) |
subjects | Etching Insulation Integrated circuit interconnections Manufacturing Minimization Printed circuits Routing Very large scale integration Wires Wiring |
title | Layer assignment for printed circuit boards and integrated circuits |
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