An SEU resistant 256K SOI SRAM

• Published in: IEEE transactions on nuclear science 1992-12, Vol.39 (6), p.2121-2125
• Main Authors: HITE, L. R, LU, H, HOUSTON, T. W, HURTA, D. S, BAILEY, W. E
• Format: Article
• Language: English
• Subjects: Applied sciences; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/23.211411

A novel SEU (single event upset) resistant SRAM (static random access memory) cell has been implemented in a 256K SOI (silicon on insulator) SRAM that has attractive performance characteristics over the military temperature range of -55 to +125 C. These include worst-case access time of 40 ns with an active power of only 150 mW at 25 MHz, and a worst-case minimum WRITE pulse width of 20 ns. Measured SEU performance gives an Adams 10 percent worst-case error rate of 3.4 x 10 exp -11 errors/bit-day using the CRUP code with a conservative first-upset LET threshold. Modeling does show that higher bipolar gain than that measured on a sample from the SRAM lot would produce a lower error rate. Measurements show the worst-case supply voltage for SEU to be 5.5 V. Analysis has shown this to be primarily caused by the drain voltage dependence of the beta of the SOI parasitic bipolar transistor. Based on this, SEU experiments with SOI devices should include measurements as a function of supply voltage, rather than the traditional 4.5 V, to determine the worst-case condition. (Author)