An implementation of high-speed decoder for double-error-correcting binary BCH codes in programmable logic array chip

A new type of decoder for double-error-correcting binary BCH codes is presented. The simple and regular control clock signals of the decoder can be directly extracted from the line signals. The decoder needs only n clock cycles to decode one received word, where n is the block length of the code. A...

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Bibliographic Details
Published in:Journal of the Chinese Institute of Engineers 1990-09, Vol.13 (6), p.665-672
Main Authors: Wei, Shyue-Win, Wei, Che-Ho, Wang, Liu-Sheng
Format: Article
Language:English
Subjects:
circuits and system
codes and decoding
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Summary:A new type of decoder for double-error-correcting binary BCH codes is presented. The simple and regular control clock signals of the decoder can be directly extracted from the line signals. The decoder needs only n clock cycles to decode one received word, where n is the block length of the code. A (31, 21, 5) BCH decoder is used as a hardware implementation example to illustrate the operation principle. The decoder can work at a data rate of up to 3.4Mbits/sec when it is implemented in a programmable Logic Cell Array (LCA) chip.
ISSN:0253-3839
2158-7299
DOI:10.1080/02533839.1990.9677298