Processing element design for a parallel computer

A study has been made of how cost-effectiveness due to the improvement of VLSI technology can apply to a scientific computer system without performance loss. The result is a parallel computer, ADENA (Alternating Direction Edition Nexus Array), with a core consisting of four kinds of VLSI chips, two...

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Bibliographic Details
Published in:IEEE MICRO 1990-04, Vol.10 (2), p.26-38
Main Authors: Kaneko, K., Nakajima, M., Kakakura, Y., Nishikawa, J., Okabayashi, I., Kadota, H.
Format: Article
Language:English
Subjects:
CMOS technology
Concurrent computing
Graphics
High performance computing
Microprocessors
Parallel processing
Performance analysis
Process design
Vector processors
Very large scale integration
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Summary:A study has been made of how cost-effectiveness due to the improvement of VLSI technology can apply to a scientific computer system without performance loss. The result is a parallel computer, ADENA (Alternating Direction Edition Nexus Array), with a core consisting of four kinds of VLSI chips, two for processor elements (PES) and two for the interprocessor network (plus some memory chips). An overview of ADENA and an analysis of its performance are given. The design considerations for the PEs incorporated in ADENA are discussed. The factors that limit performance in a parallel processing environment are analyzed, and the measures employed to improve these factors at the LSI design level are described. The 42.6 sq cm CMOS PEs reach a peak performance of 20 MFLOPS and a 256-PE ADENA 1.5 GFLOPS has been achieved and 300 to 400 MFLOPS for PDE applications.< >
ISSN:0272-1732
1937-4143
DOI:10.1109/40.52945