Self-aligned counter well-doping technology utilizing channeling ion implantation and its application to 0.25 mu m CMOS process

A new self-aligned counter doping technology intentionally utilizing channeling effect of ion implantation is presented. A 50% - 70% reduction of junction capacitance is achieved. Further, a 18.3% improvement in simulated propagation delay time is demonstrated for 0.25 mu m CMOS inverter chain under...

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Bibliographic Details
Main Authors: Nakamura, Hiroyuki, Horiuchi, Tadahiko
Format: Conference Proceeding
Language:English
Online Access:Get full text
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Summary:A new self-aligned counter doping technology intentionally utilizing channeling effect of ion implantation is presented. A 50% - 70% reduction of junction capacitance is achieved. Further, a 18.3% improvement in simulated propagation delay time is demonstrated for 0.25 mu m CMOS inverter chain under 0.9 V operation.
ISSN:0743-1562