F-RISC/I: A 32 bit RISC processor implemented in GaAs HMESFET SBFL

F-RISC/I, a reduced version of a fast RISC microprocessor, has been designed and fabricated using IBM's SBFL standard cell library and Rockwell International's 0.7 /spl mu/m HMESFET technology. F-RISC/I was designed in six months by two designers using commercial design automation tools. S...

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Bibliographic Details
Main Authors: Tien, C.K., Lewis, K., Philhower, R., Greub, H.J., McDonald, J.F.
Format: Conference Proceeding
Language:English
Subjects:
Circuit simulation
Circuit synthesis
Circuit testing
Computational modeling
Computer architecture
Design automation
Gallium arsenide
Libraries
Microprocessors
Reduced instruction set computing
Online Access:Request full text
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Summary:F-RISC/I, a reduced version of a fast RISC microprocessor, has been designed and fabricated using IBM's SBFL standard cell library and Rockwell International's 0.7 /spl mu/m HMESFET technology. F-RISC/I was designed in six months by two designers using commercial design automation tools. Simulations have shown 400 MHz operation. The chip contains 92,340 transistors on a 7/spl times/7 mm/sup 2/ die and dissipates 3.8 W. The F-RISC/I processor exemplifies the CPU architecture, circuit design, and testing developed to fully take advantage of GaAs technology for high speed computing.< >
DOI:10.1109/GAAS.1993.394482