High-performance devices for a 0.15- mu m CMOS technology

Devices have been designed and fabricated in a CMOS technology with a nominal channel length of 0.15 mu m and minimum channel length below 0.1 mu m. In order to minimize short-channel effects (SCEs) down to channel lengths below 0.1 mu m, highly nonuniform channel dopings (obtained by indium and ant...

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Bibliographic Details
Published in:IEEE electron device letters 1993-10, Vol.14 (10), p.466-468
Main Authors: Shahidi, G.G., Warnock, J., Fischer, S., McFarland, P.A., Acovic, A., Subbanna, S., Ganin, E., Crabbe, E., Comfort, J., Sun, J.Y.-C., Ning, T.H., Davari, B.
Format: Article
Language:English
Subjects:
Applied sciences
Capacitance
CMOS process
CMOS technology
Compound structure devices
Delay
Doping
Electronics
Exact sciences and technology
Implants
Indium
Lifting equipment
MOS devices
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Sun
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Summary:Devices have been designed and fabricated in a CMOS technology with a nominal channel length of 0.15 mu m and minimum channel length below 0.1 mu m. In order to minimize short-channel effects (SCEs) down to channel lengths below 0.1 mu m, highly nonuniform channel dopings (obtained by indium and antimony channel implants) and shallow source-drain extensions/halo (by In and Sb preamorphization and low-energy As and BF/sub 2/ implant were used. Maximum high V/sub DS/ threshold rolloff was 250 mV at effective channel length of 0.06 mu m. For the minimum channel length of 0.1 mu m, the loaded (FI=FO=3, C=240 fF) and unloaded delays were 150 and 25 ps, respectively.< >
ISSN:0741-3106
1558-0563
DOI:10.1109/55.244732