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Test set compaction for combinational circuits

Test set compaction for combinational circuits is studied in this paper. Two active compaction methods based on essential faults are developed to reduce a given test set. The special feature is that the given test set will be adaptively renewed to increase the chance of compaction. In the first meth...

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Published in:IEEE transactions on computer-aided design of integrated circuits and systems 1995-11, Vol.14 (11), p.1370-1378
Main Authors: Chang, Jau-Shien, Lin, Chen-Shang
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description Test set compaction for combinational circuits is studied in this paper. Two active compaction methods based on essential faults are developed to reduce a given test set. The special feature is that the given test set will be adaptively renewed to increase the chance of compaction. In the first method, forced pair-merging, pairs of patterns are merged by modifying their incompatible specified bits without sacrificing the original fault coverage. The other method, essential fault pruning, achieves further compaction from removal of a pattern by modifying other patterns of the test set to detect the essential faults of the target pattern. With these two developed methods, the compacted test size on the ISCAS'85 benchmark circuits is smaller than that of COMPACTEST by more than 20%, and 12% smaller than that by ROTCO+COMPACTEST.< >
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ispartof IEEE transactions on computer-aided design of integrated circuits and systems, 1995-11, Vol.14 (11), p.1370-1378
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1937-4151
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source IEEE Electronic Library (IEL) Journals
subjects Applied sciences
Benchmark testing
Buffer storage
Circuit faults
Circuit testing
Combinational circuits
Compaction
Design. Technologies. Operation analysis. Testing
Electrical fault detection
Electronics
Exact sciences and technology
Fault detection
Integrated circuit testing
Integrated circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Test pattern generators
title Test set compaction for combinational circuits
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