Timing verification of dynamic circuits

• Main Authors: Venkat, Kumar, Chen, Liang, Lin, Ichiang, Mistry, Piyush, Madhani, Pravin, Sato, Katsuya
• Format: Conference Proceeding
• Language: English
• ISSN: 0886-5930

A complete set of algorithmic rules is presented for timing verification of domino-style precharge logic circuits. These rules include identification of dynamic nodes in a circuit, generation of timing constraints based on the operating environment of a dynamic gate, and verification of the timing constraints as part of a complete timing verification process. An important part of this approach is propagation of gated-clock pulses which are used extensively in dynamic circuits. The algorithms have been implemented in a new static timing verifier called MTV (Mips Timing Verifier) which is targeted towards verification of custom microprocessor circuits. MTV has been demonstrated to be useful on a number of real-world custom circuits.