Loading…
A DDS synthesizer with digital time domain interpolator
A DDS type circuit structure for producing numerically programmable square wave clock signal is presented. The high speed D/A converter needed in conventional DDS systems is replaced by an N tap delay line time domain interpolator that effectively increases the sampling rate by a factor of N. Thus t...
Saved in:
Published in: | Analog integrated circuits and signal processing 2001-04, Vol.27 (1-2), p.109-116 |
---|---|
Main Authors: | , , , |
Format: | Article |
Language: | English |
Online Access: | Get full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
cited_by | |
---|---|
cites | |
container_end_page | 116 |
container_issue | 1-2 |
container_start_page | 109 |
container_title | Analog integrated circuits and signal processing |
container_volume | 27 |
creator | Rahkonen, T Eksyma, H Mantyniemi, A Repo, H |
description | A DDS type circuit structure for producing numerically programmable square wave clock signal is presented. The high speed D/A converter needed in conventional DDS systems is replaced by an N tap delay line time domain interpolator that effectively increases the sampling rate by a factor of N. Thus the circuit can be used up to full clock rate without image filtering. A prototype IC with clock frequency of 30 MHz, 5 bit interpolator and SFDR of -40 dBc up to 10 MHz and -33 dBc up to 15 MHz has been designed and tested. |
format | article |
fullrecord | <record><control><sourceid>proquest</sourceid><recordid>TN_cdi_proquest_miscellaneous_26100031</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>26100031</sourcerecordid><originalsourceid>FETCH-LOGICAL-p184t-53c25b894102d3b8b387d1fdf52772bc82dbf28c6ff9bcf4ba3721be363889713</originalsourceid><addsrcrecordid>eNotz7tOwzAUgGEPIFEK7-CJLZJ9ThI7Y9VykyoxAHPlyzE1cuIQu0Lw9CDB9G-f9J-xlRiga6RAccEuS3kXQoBqxYqpDd_tnnn5muqRSvymhX_GeuQ-vsVqEq9xJO7zaOLE41RpmXMyNS9X7DyYVOj6v2v2enf7sn1o9k_3j9vNvpmlbmvToYPO6qGVAjxabVErL4MPHSgF1mnwNoB2fQiDdaG1BhVIS9ij1oOSuGY3f-685I8TlXoYY3GUkpkon8oBevn7ghJ_AADrQn8</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>26100031</pqid></control><display><type>article</type><title>A DDS synthesizer with digital time domain interpolator</title><source>Springer Nature</source><creator>Rahkonen, T ; Eksyma, H ; Mantyniemi, A ; Repo, H</creator><creatorcontrib>Rahkonen, T ; Eksyma, H ; Mantyniemi, A ; Repo, H</creatorcontrib><description>A DDS type circuit structure for producing numerically programmable square wave clock signal is presented. The high speed D/A converter needed in conventional DDS systems is replaced by an N tap delay line time domain interpolator that effectively increases the sampling rate by a factor of N. Thus the circuit can be used up to full clock rate without image filtering. A prototype IC with clock frequency of 30 MHz, 5 bit interpolator and SFDR of -40 dBc up to 10 MHz and -33 dBc up to 15 MHz has been designed and tested.</description><identifier>ISSN: 0925-1030</identifier><language>eng</language><ispartof>Analog integrated circuits and signal processing, 2001-04, Vol.27 (1-2), p.109-116</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784</link.rule.ids></links><search><creatorcontrib>Rahkonen, T</creatorcontrib><creatorcontrib>Eksyma, H</creatorcontrib><creatorcontrib>Mantyniemi, A</creatorcontrib><creatorcontrib>Repo, H</creatorcontrib><title>A DDS synthesizer with digital time domain interpolator</title><title>Analog integrated circuits and signal processing</title><description>A DDS type circuit structure for producing numerically programmable square wave clock signal is presented. The high speed D/A converter needed in conventional DDS systems is replaced by an N tap delay line time domain interpolator that effectively increases the sampling rate by a factor of N. Thus the circuit can be used up to full clock rate without image filtering. A prototype IC with clock frequency of 30 MHz, 5 bit interpolator and SFDR of -40 dBc up to 10 MHz and -33 dBc up to 15 MHz has been designed and tested.</description><issn>0925-1030</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2001</creationdate><recordtype>article</recordtype><recordid>eNotz7tOwzAUgGEPIFEK7-CJLZJ9ThI7Y9VykyoxAHPlyzE1cuIQu0Lw9CDB9G-f9J-xlRiga6RAccEuS3kXQoBqxYqpDd_tnnn5muqRSvymhX_GeuQ-vsVqEq9xJO7zaOLE41RpmXMyNS9X7DyYVOj6v2v2enf7sn1o9k_3j9vNvpmlbmvToYPO6qGVAjxabVErL4MPHSgF1mnwNoB2fQiDdaG1BhVIS9ij1oOSuGY3f-685I8TlXoYY3GUkpkon8oBevn7ghJ_AADrQn8</recordid><startdate>20010401</startdate><enddate>20010401</enddate><creator>Rahkonen, T</creator><creator>Eksyma, H</creator><creator>Mantyniemi, A</creator><creator>Repo, H</creator><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>20010401</creationdate><title>A DDS synthesizer with digital time domain interpolator</title><author>Rahkonen, T ; Eksyma, H ; Mantyniemi, A ; Repo, H</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p184t-53c25b894102d3b8b387d1fdf52772bc82dbf28c6ff9bcf4ba3721be363889713</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2001</creationdate><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Rahkonen, T</creatorcontrib><creatorcontrib>Eksyma, H</creatorcontrib><creatorcontrib>Mantyniemi, A</creatorcontrib><creatorcontrib>Repo, H</creatorcontrib><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Analog integrated circuits and signal processing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Rahkonen, T</au><au>Eksyma, H</au><au>Mantyniemi, A</au><au>Repo, H</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A DDS synthesizer with digital time domain interpolator</atitle><jtitle>Analog integrated circuits and signal processing</jtitle><date>2001-04-01</date><risdate>2001</risdate><volume>27</volume><issue>1-2</issue><spage>109</spage><epage>116</epage><pages>109-116</pages><issn>0925-1030</issn><abstract>A DDS type circuit structure for producing numerically programmable square wave clock signal is presented. The high speed D/A converter needed in conventional DDS systems is replaced by an N tap delay line time domain interpolator that effectively increases the sampling rate by a factor of N. Thus the circuit can be used up to full clock rate without image filtering. A prototype IC with clock frequency of 30 MHz, 5 bit interpolator and SFDR of -40 dBc up to 10 MHz and -33 dBc up to 15 MHz has been designed and tested.</abstract><tpages>8</tpages></addata></record> |
fulltext | fulltext |
identifier | ISSN: 0925-1030 |
ispartof | Analog integrated circuits and signal processing, 2001-04, Vol.27 (1-2), p.109-116 |
issn | 0925-1030 |
language | eng |
recordid | cdi_proquest_miscellaneous_26100031 |
source | Springer Nature |
title | A DDS synthesizer with digital time domain interpolator |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T23%3A50%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20DDS%20synthesizer%20with%20digital%20time%20domain%20interpolator&rft.jtitle=Analog%20integrated%20circuits%20and%20signal%20processing&rft.au=Rahkonen,%20T&rft.date=2001-04-01&rft.volume=27&rft.issue=1-2&rft.spage=109&rft.epage=116&rft.pages=109-116&rft.issn=0925-1030&rft_id=info:doi/&rft_dat=%3Cproquest%3E26100031%3C/proquest%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-p184t-53c25b894102d3b8b387d1fdf52772bc82dbf28c6ff9bcf4ba3721be363889713%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=26100031&rft_id=info:pmid/&rfr_iscdi=true |