Offset-trimming bit-line sensing scheme for gigabit-scale DRAM's

A new offset-trimming bit-line sensing scheme is described which is suitable for gigabit-scale DRAM's. This sensing scheme can suppress the sensitivity degradation caused by the large electrical parameter variation of deep submicron transistors. The effective offset voltage dependence on trimmi...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1996-07, Vol.31 (7), p.1025-1028
Main Authors: Suh, Jung-Won, Rho, Kwang-Myoung, Park, Chan-Kwang, Koh, Yo-Hwan
Format: Article
Language:English
Subjects:
Analytical models
Circuits
CMOS technology
Degradation
Feedback
Inverters
MOSFETs
Random access memory
Timing
Voltage
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Description
Summary:A new offset-trimming bit-line sensing scheme is described which is suitable for gigabit-scale DRAM's. This sensing scheme can suppress the sensitivity degradation caused by the large electrical parameter variation of deep submicron transistors. The effective offset voltage dependence on trimming time is analyzed and verified with simulation results. As compared with a conventional direct sensing scheme, the proposed scheme shows remarkable improvement on the sensitivity. A test device was fabricated with a 0.25 /spl mu/m CMOS technology and its measurement results indicate the successful operation of offset-trimming.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.508216