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Molded chip scale package for high pin count
A unique molded Chip Scale Package (CSP) associated 1024 pin counts has been developed. The design and process have been optimized in order to achieve high mount density, enhanced electrical characteristic and cost competitiveness. Also, the reliability testing was performed on thermal cycling and m...
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creator | Baba, S. Tomita, Y. Matsuo, M. Matsushima, H. Ueda, N. Nakagawa, O. |
description | A unique molded Chip Scale Package (CSP) associated 1024 pin counts has been developed. The design and process have been optimized in order to achieve high mount density, enhanced electrical characteristic and cost competitiveness. Also, the reliability testing was performed on thermal cycling and moisture induced crack resistivity. Finally, enhanced electrical and thermal characteristics were calculated. |
doi_str_mv | 10.1109/ECTC.1996.550895 |
format | conference_proceeding |
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The design and process have been optimized in order to achieve high mount density, enhanced electrical characteristic and cost competitiveness. Also, the reliability testing was performed on thermal cycling and moisture induced crack resistivity. Finally, enhanced electrical and thermal characteristics were calculated.</description><subject>Chip scale packaging</subject><subject>Conductivity</subject><subject>Cost function</subject><subject>Design optimization</subject><subject>Electric variables</subject><subject>Moisture</subject><subject>Performance evaluation</subject><subject>Process design</subject><subject>Testing</subject><subject>Thermal resistance</subject><issn>0569-5503</issn><issn>2377-5726</issn><isbn>9780780332867</isbn><isbn>0780332865</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1996</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNot0DtPwzAUBWCLh0Qp3RGTJyYSrt_2iKLykIpYyhy5N3ZjSJsQtwP_nkhFOtJZPp3hEHLLoGQM3OOyWlclc06XSoF16ozMuDCmUIbrc7JwxsIUIbjV5oLMQGlXTFJckeucvwAkALMz8vDed01oKLZpoBl9F-jg8dtvA439SNu0bemQ9hT74_5wQy6j73JY_PecfD4v19Vrsfp4eaueVkXiIA6FVRuLjZbKCJRGOSG0jJYZzzjKGBAV6Mg8cgQfIG6c9xO1RkalUCov5uT-tDuM_c8x5EO9SxlD1_l96I-55po5I52Z4N0JphBCPYxp58ff-nSI-ANYmVBE</recordid><startdate>1996</startdate><enddate>1996</enddate><creator>Baba, S.</creator><creator>Tomita, Y.</creator><creator>Matsuo, M.</creator><creator>Matsushima, H.</creator><creator>Ueda, N.</creator><creator>Nakagawa, O.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>1996</creationdate><title>Molded chip scale package for high pin count</title><author>Baba, S. ; Tomita, Y. ; Matsuo, M. ; Matsushima, H. ; Ueda, N. ; Nakagawa, O.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i203t-85b8cd64573c47593364f817a12c4fecc506f1ac2c0ae0fb9aa573874f55c45a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1996</creationdate><topic>Chip scale packaging</topic><topic>Conductivity</topic><topic>Cost function</topic><topic>Design optimization</topic><topic>Electric variables</topic><topic>Moisture</topic><topic>Performance evaluation</topic><topic>Process design</topic><topic>Testing</topic><topic>Thermal resistance</topic><toplevel>online_resources</toplevel><creatorcontrib>Baba, S.</creatorcontrib><creatorcontrib>Tomita, Y.</creatorcontrib><creatorcontrib>Matsuo, M.</creatorcontrib><creatorcontrib>Matsushima, H.</creatorcontrib><creatorcontrib>Ueda, N.</creatorcontrib><creatorcontrib>Nakagawa, O.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEL</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Baba, S.</au><au>Tomita, Y.</au><au>Matsuo, M.</au><au>Matsushima, H.</au><au>Ueda, N.</au><au>Nakagawa, O.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Molded chip scale package for high pin count</atitle><btitle>1996 Proceedings 46th Electronic Components and Technology Conference</btitle><stitle>ECTC</stitle><date>1996</date><risdate>1996</risdate><spage>1251</spage><epage>1257</epage><pages>1251-1257</pages><issn>0569-5503</issn><eissn>2377-5726</eissn><isbn>9780780332867</isbn><isbn>0780332865</isbn><abstract>A unique molded Chip Scale Package (CSP) associated 1024 pin counts has been developed. The design and process have been optimized in order to achieve high mount density, enhanced electrical characteristic and cost competitiveness. Also, the reliability testing was performed on thermal cycling and moisture induced crack resistivity. Finally, enhanced electrical and thermal characteristics were calculated.</abstract><pub>IEEE</pub><doi>10.1109/ECTC.1996.550895</doi><tpages>7</tpages></addata></record> |
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identifier | ISSN: 0569-5503 |
ispartof | 1996 Proceedings 46th Electronic Components and Technology Conference, 1996, p.1251-1257 |
issn | 0569-5503 2377-5726 |
language | eng |
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source | IEEE Xplore All Conference Series |
subjects | Chip scale packaging Conductivity Cost function Design optimization Electric variables Moisture Performance evaluation Process design Testing Thermal resistance |
title | Molded chip scale package for high pin count |
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