An Integrated Hardware Array for Very High Speed Logic Simulation

• Published in: VLSI Design 1996-01, Vol.1996 (2), p.107-118
• Main Authors: Fehr, E. Scott, Szygenda, Stephen A., Ott, Granville E.
• Format: Article
• Language: English
• ISSN: 1065-514X; 1563-5171
• DOI: 10.1155/1996/13931

A hardware architecture is proposed which allows direct mapping of design simulation topology onto an acceleration platform. In order to clarify architectural principles, the simulation is confined to functional verification of unit delay, binary valued gate level logic designs. Under this approach, a rank ordered design description is executed on a massively parallel processor grid which implements an efficient and direct model of the design, similar to prototyping. Architectural innovation reduces logic complexity and execution time of boolean evaluation and fanout switching circuits, while large scale parallelism is integrated at die level to reduce cost and communication delays. The results of this research form the basis for a multiple order of magnitude improvement in reported state‐of‐the‐art cost‐performance merit for hardware gate level simulation accelerators.