32-bit superscalar microprocessor GMICRO/400 for embedded systems

This paper describes a 32-bit superscalar microprocessor GMICRO/400, based on the TRON architecture specifications. The GMICRO/400 has a dual issued instruction pipeline, a pre-jump mechanism and a high-speed memory access interface. To realize high performance in processing of series data such as f...

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Bibliographic Details
Main Authors: Korematsu, Jiro, Ueda, Tatsuya, Matsuo, Masahito, Tani, Kunio, Okumura, Naoto, Ishimi, Kouichi, Yoshida, Toyohiko, Saito, Yuichi, Hinata, Junichi
Format: Conference Proceeding
Language:English
Online Access:Get full text
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Summary:This paper describes a 32-bit superscalar microprocessor GMICRO/400, based on the TRON architecture specifications. The GMICRO/400 has a dual issued instruction pipeline, a pre-jump mechanism and a high-speed memory access interface. To realize high performance in processing of series data such as frame buffer or character-strings, the GMICRO/400 has improved the execution efficiency of multiple-operation instructions by block-data-transfer and 64-bit processing. In order to improve the task switching latency, the on-chip caches are used as a local memory in which the context blocks are stored. These techniques are suitable for realtime embedded systems, such as X-window terminals and printers. Using 0.5 mu m triple-layer metal CMOS technology, the GMICRO/400 integrates 1485 K transistors on a 108 mm super(2) die area. The GMICRO/400 achieves a processing speed of 45 MIPS at 40 MHz.
ISSN:1063-6749