Performance and reliability aspects of FOND: a new deep submicron CMOS device concept

The electrical performance and the hot-carrier degradation behavior of a new type of fully overlapped device called FOND (Fully Overlapped Nitride-etch defined Device) is analyzed and compared to that of conventional LDD devices. Similar current driveability is found for the FOND devices compared to...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on electron devices 1996-09, Vol.43 (9), p.1407-1415
Main Authors: Bellens, R., Van den Bosch, G., Habas, P., Mieville, J.-P., Badenes, G., Clerix, A., Groeseneken, G., Deferm, L., Maes, H.E.
Format: Article
Language:English
Subjects:
Capacitance
Degradation
Electric resistance
Hot carriers
Implants
MOSFETs
Numerical models
Performance analysis
Senior members
Voltage-controlled oscillators
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The electrical performance and the hot-carrier degradation behavior of a new type of fully overlapped device called FOND (Fully Overlapped Nitride-etch defined Device) is analyzed and compared to that of conventional LDD devices. Similar current driveability is found for the FOND devices compared to conventional LDD devices although in the FOND device significantly smaller concentrations are used for the lightly doped n/sup -/-regions. For the overlapped device, a higher gate and overlap capacitance is found, originating from a larger poly length and self-alignment of the junction implant to the poly. For identical voltage conditions, this is reflected in a somewhat lower ring oscillator speed, compared to the LDD case. Concerning reliability, it is shown that deep submicron FOND devices can easily exceed the lifetime of the conventional LDD devices by two orders of magnitude. Based on experimental and simulation results, this higher hot-carrier resistance is explained by a smaller hot-carrier generation and a lower sensitivity of the overlapped device to hot-carrier damage. For the nMOS transistors, the lower generation of damage is the result of the lower lateral electric field due to the low n/sup -/ concentration and the overlap of the polysilicon gate on the n/sup -/ region while the suppressed sensitivity is due to the complete overlap. Compared to LDD devices, the use of fully overlapped devices creates a wider process and reliability margin that can be used to optimize other electrical parameters.
ISSN:0018-9383
1557-9646
DOI:10.1109/16.535326