VLSI implementation of digit-serial arithmetic modules

This article describes an implementation of arithmetic modules which is based on the transmission of arithmetic data serially one digit at a time. For some applications bit-serial architectures may be too slow, and bit-parallel architectures may be faster than necessary and require too much hardware...

Full description

Saved in:
Bibliographic Details
Published in:Microprocessing and microprogramming 1993, Vol.39 (2), p.251-254
Main Authors: Bisdounis, L., Metafas, D.E., Maras, A.M., Mavridis, C.
Format: Article
Language:English
Citations: Items that this one cites
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This article describes an implementation of arithmetic modules which is based on the transmission of arithmetic data serially one digit at a time. For some applications bit-serial architectures may be too slow, and bit-parallel architectures may be faster than necessary and require too much hardware. The desired sample rate in these applications can be achieved using the digit-serial approach.
ISSN:0165-6074
DOI:10.1016/0165-6074(93)90099-7