Innovative structures for CMOS combinational gates synthesis

• Published in: IEEE transactions on computers 1994-04, Vol.43 (4), p.385-399
• Main Authors: Buonanno, G., Sciuto, D., Stefanelli, R.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit synthesis; CMOS logic circuits; Delay; Design optimization; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuit interconnections; Integrated circuits; Logic gates; Minimization methods; Network synthesis; Programmable logic arrays; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Variable structure systems
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/12.278478

Design of multiple outputs CMOS combinational gates is studied. Two techniques for minimization of multiple output functions at the switching level are introduced. These techniques are based on innovative transistor interconnection structures named Delta and Lambda networks. The two techniques can be combined together to obtain further area reductions. Different synthesis algorithms are discussed, from exhaustive enumeration to branch and bound to heuristic techniques allowing to speed up the synthesis process. Simulation results for synthesis are introduced to compare the different algorithms. Design examples are also provided. Electrical simulations show that the dynamic behavior of such structures is comparable to the traditional static or domino implementations (obviously the new and traditional structures have the same static behavior).< >