Arriving at a unified model for hot-carrier degradation in MOSFET's through gate-to-drain capacitance measurement

Hot carrier degradation of sub-micron n-channel and p-channel MOSFET's from a CMOS process was investigated using small-signal gate-to-drain capacitance and charge pumping measurements for three different stress conditions. For both devices the worst case degradation was found to be due to the...

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Bibliographic Details
Published in:IEEE transactions on electron devices 1994-12, Vol.41 (12), p.2423-2429
Main Authors: Ghodsi, R., Yew-Tong Yeow, Chung Ho Ling, Alam, M.K.
Format: Article
Language:English
Subjects:
Applied sciences
Capacitance measurement
Charge measurement
Charge pumps
CMOS process
Current measurement
Degradation
Electronics
Exact sciences and technology
Hot carriers
Interface states
Photonic band gap
Semiconductor device modeling
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Transistors
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Summary:Hot carrier degradation of sub-micron n-channel and p-channel MOSFET's from a CMOS process was investigated using small-signal gate-to-drain capacitance and charge pumping measurements for three different stress conditions. For both devices the worst case degradation was found to be due to the trapping of majority carriers and the creation of acceptor interface states, mainly in the upper half of the bandgap. It was concluded that the trapping of carriers and generation of interface states are separate processes. The effect of the donor interface states in the lower half of the bandgap necessary to associate the interface states with the P/sub bo/ dangling bond model was not observed. A possible cause is suggested.< >
ISSN:0018-9383
1557-9646
DOI:10.1109/16.337459