Area-time efficient modulo 2 super(n) - 1 adder design

In this paper the design of modulo 2 super(n) - 1 adders is discussed. Two new design procedures are given, based on the one-level and the two-level carry look-ahead addition algorithms. The adders designed according to the procedures proposed in this paper are significantly more efficient, with res...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 1994-01, Vol.41 (7), p.463-467
Main Authors: Efstathiou, C, Nikolos, D, Kalamatianos, J
Format: Article
Language:English
Online Access:Get full text
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Summary:In this paper the design of modulo 2 super(n) - 1 adders is discussed. Two new design procedures are given, based on the one-level and the two-level carry look-ahead addition algorithms. The adders designed according to the procedures proposed in this paper are significantly more efficient, with respect to speed and the cost function area-time product, than the corresponding adders already known from open literature.
ISSN:1057-7130