Vertical MOS-gated pin-diodes: MOS-gated tunneling transistors in Si(100) and Si(111)

• Published in: Thin solid films 2000-12, Vol.380 (1), p.154-157
• Main Authors: Schulze, J, Fink, C, Sulima, T, Eisele, I, Hansch, W
• Format: Article
• Language: English
• Subjects: Applied sciences; B surface phase; Electronics; Exact sciences and technology; MBE; Pin-diode; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors; Tunneling-FET; Vertical MOSFET; δ-Doping
• ISSN: 0040-6090; 1879-2731
• DOI: 10.1016/S0040-6090(00)01492-9

Tunneling devices are an interesting alternative to conventional MOS-devices due to their high speed switching capabilities. Recently, it was shown that tunneling transistors based on vertical MOS-gated pin-diodes can be fabricated. The pin-diodes themselves were grown by means of UHV-MBE on highly n +-doped Si(100)-substrates with a 100 nm thick intrinsic channel region. The top contact was formed by the deposition of a highly-doped B δ-layer with a peak doping amount of approximately 10 21 cm −3 for the necessary abrupt pn-junction and 300-nm p +-contact region. At a low supply voltage of −0.2 V, a current gain of three orders of magnitude with saturation behavior is achieved [1]. In the present contribution, we have shown the influence of the amount of B in the δ-layer and of the abruptness of the drain-channel-junction on the transistor behavior. For that, we have discussed the characteristics of MOS-gated pin-diodes on Si(111) with ultra-sharp B δ's with a peak doping amount between 10 20 and 10 21 cm −3 and a peak width