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A 150MHz graphics rendering processor with 256Mb embedded DRAM
A 150 MHz graphics rendering processor with 256 Mb embedded dynamic random access storage (DRAM) was proposed. The graphics rendering processor for high-resolution computer graphics was based on computer enetertainment system architecture. A careful electrical design of large scale RC networks and d...
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| Language: | English |
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| creator | Khan, A K Magoshi, H Matsumoto, T Fujita, J-I Furuhashi, M Imai, M Kurose, Y Sato, M Sato, K Yamashita, Y Kwan, K Le, D-N Yu, J H Nguyen, T Yang, S |
| description | A 150 MHz graphics rendering processor with 256 Mb embedded dynamic random access storage (DRAM) was proposed. The graphics rendering processor for high-resolution computer graphics was based on computer enetertainment system architecture. A careful electrical design of large scale RC networks and design technology was presented for the characterization of interconnect-dominated timing and signal integrity. Net-to-net coupling-induced delay variations was addressed by annalyzing all nets for crosstalk immunity. |
| format | conference_proceeding |
| fullrecord | <record><control><sourceid>proquest</sourceid><recordid>TN_cdi_proquest_miscellaneous_26635103</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>26635103</sourcerecordid><originalsourceid>FETCH-LOGICAL-p99t-25a1324320a1845edeaa29472d3d880c642c5b2fb2e2bc6671b566031b7af4603</originalsourceid><addsrcrecordid>eNotjstKw0AUQGeh0Fr9h1m5C9y580hmI4T6qNAgSPdlHjdtSprEmRTBr7egq3NWh3PDliCsLIyWsGB3OZ8AQFtTLdlTzYWGZvPDD8lNxy5knmiIlLrhwKc0Bsp5TPy7m48ctWk8p7OnGCny58-6uWe3reszPfxzxXavL7v1pth-vL2v620xWTsXqJ2QqCSCE5XSFMk5tKrEKGNVQTAKg_bYeiT0wZhSeG0MSOFL16qrrNjjX_Z69HWhPO_PXQ7U926g8ZL3aIzUAqT8BYNxQkA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype><pqid>26635103</pqid></control><display><type>conference_proceeding</type><title>A 150MHz graphics rendering processor with 256Mb embedded DRAM</title><source>IEEE Xplore All Conference Series</source><creator>Khan, A K ; Magoshi, H ; Matsumoto, T ; Fujita, J-I ; Furuhashi, M ; Imai, M ; Kurose, Y ; Sato, M ; Sato, K ; Yamashita, Y ; Kwan, K ; Le, D-N ; Yu, J H ; Nguyen, T ; Yang, S</creator><creatorcontrib>Khan, A K ; Magoshi, H ; Matsumoto, T ; Fujita, J-I ; Furuhashi, M ; Imai, M ; Kurose, Y ; Sato, M ; Sato, K ; Yamashita, Y ; Kwan, K ; Le, D-N ; Yu, J H ; Nguyen, T ; Yang, S</creatorcontrib><description>A 150 MHz graphics rendering processor with 256 Mb embedded dynamic random access storage (DRAM) was proposed. The graphics rendering processor for high-resolution computer graphics was based on computer enetertainment system architecture. A careful electrical design of large scale RC networks and design technology was presented for the characterization of interconnect-dominated timing and signal integrity. Net-to-net coupling-induced delay variations was addressed by annalyzing all nets for crosstalk immunity.</description><identifier>ISSN: 0193-6530</identifier><language>eng</language><ispartof>Digest of technical papers - IEEE International Solid-State Circuits Conference, 2001</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784</link.rule.ids></links><search><creatorcontrib>Khan, A K</creatorcontrib><creatorcontrib>Magoshi, H</creatorcontrib><creatorcontrib>Matsumoto, T</creatorcontrib><creatorcontrib>Fujita, J-I</creatorcontrib><creatorcontrib>Furuhashi, M</creatorcontrib><creatorcontrib>Imai, M</creatorcontrib><creatorcontrib>Kurose, Y</creatorcontrib><creatorcontrib>Sato, M</creatorcontrib><creatorcontrib>Sato, K</creatorcontrib><creatorcontrib>Yamashita, Y</creatorcontrib><creatorcontrib>Kwan, K</creatorcontrib><creatorcontrib>Le, D-N</creatorcontrib><creatorcontrib>Yu, J H</creatorcontrib><creatorcontrib>Nguyen, T</creatorcontrib><creatorcontrib>Yang, S</creatorcontrib><title>A 150MHz graphics rendering processor with 256Mb embedded DRAM</title><title>Digest of technical papers - IEEE International Solid-State Circuits Conference</title><description>A 150 MHz graphics rendering processor with 256 Mb embedded dynamic random access storage (DRAM) was proposed. The graphics rendering processor for high-resolution computer graphics was based on computer enetertainment system architecture. A careful electrical design of large scale RC networks and design technology was presented for the characterization of interconnect-dominated timing and signal integrity. Net-to-net coupling-induced delay variations was addressed by annalyzing all nets for crosstalk immunity.</description><issn>0193-6530</issn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2001</creationdate><recordtype>conference_proceeding</recordtype><recordid>eNotjstKw0AUQGeh0Fr9h1m5C9y580hmI4T6qNAgSPdlHjdtSprEmRTBr7egq3NWh3PDliCsLIyWsGB3OZ8AQFtTLdlTzYWGZvPDD8lNxy5knmiIlLrhwKc0Bsp5TPy7m48ctWk8p7OnGCny58-6uWe3reszPfxzxXavL7v1pth-vL2v620xWTsXqJ2QqCSCE5XSFMk5tKrEKGNVQTAKg_bYeiT0wZhSeG0MSOFL16qrrNjjX_Z69HWhPO_PXQ7U926g8ZL3aIzUAqT8BYNxQkA</recordid><startdate>20010101</startdate><enddate>20010101</enddate><creator>Khan, A K</creator><creator>Magoshi, H</creator><creator>Matsumoto, T</creator><creator>Fujita, J-I</creator><creator>Furuhashi, M</creator><creator>Imai, M</creator><creator>Kurose, Y</creator><creator>Sato, M</creator><creator>Sato, K</creator><creator>Yamashita, Y</creator><creator>Kwan, K</creator><creator>Le, D-N</creator><creator>Yu, J H</creator><creator>Nguyen, T</creator><creator>Yang, S</creator><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>20010101</creationdate><title>A 150MHz graphics rendering processor with 256Mb embedded DRAM</title><author>Khan, A K ; Magoshi, H ; Matsumoto, T ; Fujita, J-I ; Furuhashi, M ; Imai, M ; Kurose, Y ; Sato, M ; Sato, K ; Yamashita, Y ; Kwan, K ; Le, D-N ; Yu, J H ; Nguyen, T ; Yang, S</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p99t-25a1324320a1845edeaa29472d3d880c642c5b2fb2e2bc6671b566031b7af4603</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2001</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Khan, A K</creatorcontrib><creatorcontrib>Magoshi, H</creatorcontrib><creatorcontrib>Matsumoto, T</creatorcontrib><creatorcontrib>Fujita, J-I</creatorcontrib><creatorcontrib>Furuhashi, M</creatorcontrib><creatorcontrib>Imai, M</creatorcontrib><creatorcontrib>Kurose, Y</creatorcontrib><creatorcontrib>Sato, M</creatorcontrib><creatorcontrib>Sato, K</creatorcontrib><creatorcontrib>Yamashita, Y</creatorcontrib><creatorcontrib>Kwan, K</creatorcontrib><creatorcontrib>Le, D-N</creatorcontrib><creatorcontrib>Yu, J H</creatorcontrib><creatorcontrib>Nguyen, T</creatorcontrib><creatorcontrib>Yang, S</creatorcontrib><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Khan, A K</au><au>Magoshi, H</au><au>Matsumoto, T</au><au>Fujita, J-I</au><au>Furuhashi, M</au><au>Imai, M</au><au>Kurose, Y</au><au>Sato, M</au><au>Sato, K</au><au>Yamashita, Y</au><au>Kwan, K</au><au>Le, D-N</au><au>Yu, J H</au><au>Nguyen, T</au><au>Yang, S</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 150MHz graphics rendering processor with 256Mb embedded DRAM</atitle><btitle>Digest of technical papers - IEEE International Solid-State Circuits Conference</btitle><date>2001-01-01</date><risdate>2001</risdate><issn>0193-6530</issn><abstract>A 150 MHz graphics rendering processor with 256 Mb embedded dynamic random access storage (DRAM) was proposed. The graphics rendering processor for high-resolution computer graphics was based on computer enetertainment system architecture. A careful electrical design of large scale RC networks and design technology was presented for the characterization of interconnect-dominated timing and signal integrity. Net-to-net coupling-induced delay variations was addressed by annalyzing all nets for crosstalk immunity.</abstract></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0193-6530 |
| ispartof | Digest of technical papers - IEEE International Solid-State Circuits Conference, 2001 |
| issn | 0193-6530 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_26635103 |
| source | IEEE Xplore All Conference Series |
| title | A 150MHz graphics rendering processor with 256Mb embedded DRAM |
| url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T14%3A20%3A52IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20150MHz%20graphics%20rendering%20processor%20with%20256Mb%20embedded%20DRAM&rft.btitle=Digest%20of%20technical%20papers%20-%20IEEE%20International%20Solid-State%20Circuits%20Conference&rft.au=Khan,%20A%20K&rft.date=2001-01-01&rft.issn=0193-6530&rft_id=info:doi/&rft_dat=%3Cproquest%3E26635103%3C/proquest%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-p99t-25a1324320a1845edeaa29472d3d880c642c5b2fb2e2bc6671b566031b7af4603%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=26635103&rft_id=info:pmid/&rfr_iscdi=true |