DCT hardware structure for sequentially presented data

This paper shows that a fast DCT algorithm is mapped into a hardware structure that consists of log 2 N modules. Such a hardware structure can be used for bit-serial word-serial or word-serial bit-parallel implementation. Compared to other methods of hardware implementation, the proposed one provide...

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Bibliographic Details
Published in:Signal processing 2001-11, Vol.81 (11), p.2333-2342
Main Authors: Tan, T.C, Bi, Guoan, Zeng, Yonghong, Tan, H.N
Format: Article
Language:English
Subjects:
Applied sciences
Bit-serial processing
Detection, estimation, filtering, equalization, prediction
Discrete cosine transform
Exact sciences and technology
Information, signal and communications theory
Signal and communications theory
Signal, noise
Telecommunications and information theory
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Summary:This paper shows that a fast DCT algorithm is mapped into a hardware structure that consists of log 2 N modules. Such a hardware structure can be used for bit-serial word-serial or word-serial bit-parallel implementation. Compared to other methods of hardware implementation, the proposed one provides a naturally interface with sequentially presented input data, achieves a high utilization of hardware, requires a low processing latency and has a modular architecture that can be extended to support different transform sizes.
ISSN:0165-1684
1872-7557
DOI:10.1016/S0165-1684(01)00113-X