DCT hardware structure for sequentially presented data

This paper shows that a fast DCT algorithm is mapped into a hardware structure that consists of log 2 N modules. Such a hardware structure can be used for bit-serial word-serial or word-serial bit-parallel implementation. Compared to other methods of hardware implementation, the proposed one provide...

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Published in:Signal processing 2001-11, Vol.81 (11), p.2333-2342
Main Authors: Tan, T.C, Bi, Guoan, Zeng, Yonghong, Tan, H.N
Format: Article
Language:English
Subjects:
Applied sciences
Bit-serial processing
Detection, estimation, filtering, equalization, prediction
Discrete cosine transform
Exact sciences and technology
Information, signal and communications theory
Signal and communications theory
Signal, noise
Telecommunications and information theory
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cited_by cdi_FETCH-LOGICAL-c368t-44d80b653c11433e1f73ddd21df38102e33a26a20ae5a909ca8ed474820d25713
cites cdi_FETCH-LOGICAL-c368t-44d80b653c11433e1f73ddd21df38102e33a26a20ae5a909ca8ed474820d25713
container_end_page 2342
container_issue 11
container_start_page 2333
container_title Signal processing
container_volume 81
creator Tan, T.C
Bi, Guoan
Zeng, Yonghong
Tan, H.N
description This paper shows that a fast DCT algorithm is mapped into a hardware structure that consists of log 2 N modules. Such a hardware structure can be used for bit-serial word-serial or word-serial bit-parallel implementation. Compared to other methods of hardware implementation, the proposed one provides a naturally interface with sequentially presented input data, achieves a high utilization of hardware, requires a low processing latency and has a modular architecture that can be extended to support different transform sizes.
doi_str_mv 10.1016/S0165-1684(01)00113-X
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fullrecord <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_26685260</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><els_id>S016516840100113X</els_id><sourcerecordid>26685260</sourcerecordid><originalsourceid>FETCH-LOGICAL-c368t-44d80b653c11433e1f73ddd21df38102e33a26a20ae5a909ca8ed474820d25713</originalsourceid><addsrcrecordid>eNqFkE1LAzEQhoMoWKs_QdiLoofVTLLJpieR-gkFD1boLYzJLK5suzXZVfrvTVvRo5f5gGfmnXkZOwZ-ARz05XMKKgdtijMO55wDyHy2wwZgSpGXSpW7bPCL7LODGN95oqTmA6ZvxtPsDYP_wkBZ7ELvuj5VVRuySB89Lboam2aVLQPF1JDPPHZ4yPYqbCId_eQhe7m7nY4f8snT_eP4epI7qU2XF4U3_FUr6QAKKQmqUnrvBfhKGuCCpEShUXAkhSM-cmjIF2VhBPdClSCH7HS7dxnadEzs7LyOjpoGF9T20QqtjRKaJ1BtQRfaGANVdhnqOYaVBW7XLtmNS3ZtgeVgNy7ZWZo7-RHA6LCpAi5cHf-GC5BcwyhxV1uO0refNQUbXU0LR74O5Drr2_ofpW-ronqs</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>26685260</pqid></control><display><type>article</type><title>DCT hardware structure for sequentially presented data</title><source>ScienceDirect Freedom Collection 2022-2024</source><creator>Tan, T.C ; Bi, Guoan ; Zeng, Yonghong ; Tan, H.N</creator><creatorcontrib>Tan, T.C ; Bi, Guoan ; Zeng, Yonghong ; Tan, H.N</creatorcontrib><description>This paper shows that a fast DCT algorithm is mapped into a hardware structure that consists of log 2 N modules. Such a hardware structure can be used for bit-serial word-serial or word-serial bit-parallel implementation. Compared to other methods of hardware implementation, the proposed one provides a naturally interface with sequentially presented input data, achieves a high utilization of hardware, requires a low processing latency and has a modular architecture that can be extended to support different transform sizes.</description><identifier>ISSN: 0165-1684</identifier><identifier>EISSN: 1872-7557</identifier><identifier>DOI: 10.1016/S0165-1684(01)00113-X</identifier><identifier>CODEN: SPRODR</identifier><language>eng</language><publisher>Amsterdam: Elsevier B.V</publisher><subject>Applied sciences ; Bit-serial processing ; Detection, estimation, filtering, equalization, prediction ; Discrete cosine transform ; Exact sciences and technology ; Information, signal and communications theory ; Signal and communications theory ; Signal, noise ; Telecommunications and information theory</subject><ispartof>Signal processing, 2001-11, Vol.81 (11), p.2333-2342</ispartof><rights>2001 Elsevier Science B.V.</rights><rights>2002 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c368t-44d80b653c11433e1f73ddd21df38102e33a26a20ae5a909ca8ed474820d25713</citedby><cites>FETCH-LOGICAL-c368t-44d80b653c11433e1f73ddd21df38102e33a26a20ae5a909ca8ed474820d25713</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,27924,27925</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&amp;idt=14130619$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Tan, T.C</creatorcontrib><creatorcontrib>Bi, Guoan</creatorcontrib><creatorcontrib>Zeng, Yonghong</creatorcontrib><creatorcontrib>Tan, H.N</creatorcontrib><title>DCT hardware structure for sequentially presented data</title><title>Signal processing</title><description>This paper shows that a fast DCT algorithm is mapped into a hardware structure that consists of log 2 N modules. Such a hardware structure can be used for bit-serial word-serial or word-serial bit-parallel implementation. Compared to other methods of hardware implementation, the proposed one provides a naturally interface with sequentially presented input data, achieves a high utilization of hardware, requires a low processing latency and has a modular architecture that can be extended to support different transform sizes.</description><subject>Applied sciences</subject><subject>Bit-serial processing</subject><subject>Detection, estimation, filtering, equalization, prediction</subject><subject>Discrete cosine transform</subject><subject>Exact sciences and technology</subject><subject>Information, signal and communications theory</subject><subject>Signal and communications theory</subject><subject>Signal, noise</subject><subject>Telecommunications and information theory</subject><issn>0165-1684</issn><issn>1872-7557</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2001</creationdate><recordtype>article</recordtype><recordid>eNqFkE1LAzEQhoMoWKs_QdiLoofVTLLJpieR-gkFD1boLYzJLK5suzXZVfrvTVvRo5f5gGfmnXkZOwZ-ARz05XMKKgdtijMO55wDyHy2wwZgSpGXSpW7bPCL7LODGN95oqTmA6ZvxtPsDYP_wkBZ7ELvuj5VVRuySB89Lboam2aVLQPF1JDPPHZ4yPYqbCId_eQhe7m7nY4f8snT_eP4epI7qU2XF4U3_FUr6QAKKQmqUnrvBfhKGuCCpEShUXAkhSM-cmjIF2VhBPdClSCH7HS7dxnadEzs7LyOjpoGF9T20QqtjRKaJ1BtQRfaGANVdhnqOYaVBW7XLtmNS3ZtgeVgNy7ZWZo7-RHA6LCpAi5cHf-GC5BcwyhxV1uO0refNQUbXU0LR74O5Drr2_ofpW-ronqs</recordid><startdate>20011101</startdate><enddate>20011101</enddate><creator>Tan, T.C</creator><creator>Bi, Guoan</creator><creator>Zeng, Yonghong</creator><creator>Tan, H.N</creator><general>Elsevier B.V</general><general>Elsevier Science</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>20011101</creationdate><title>DCT hardware structure for sequentially presented data</title><author>Tan, T.C ; Bi, Guoan ; Zeng, Yonghong ; Tan, H.N</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c368t-44d80b653c11433e1f73ddd21df38102e33a26a20ae5a909ca8ed474820d25713</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Applied sciences</topic><topic>Bit-serial processing</topic><topic>Detection, estimation, filtering, equalization, prediction</topic><topic>Discrete cosine transform</topic><topic>Exact sciences and technology</topic><topic>Information, signal and communications theory</topic><topic>Signal and communications theory</topic><topic>Signal, noise</topic><topic>Telecommunications and information theory</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Tan, T.C</creatorcontrib><creatorcontrib>Bi, Guoan</creatorcontrib><creatorcontrib>Zeng, Yonghong</creatorcontrib><creatorcontrib>Tan, H.N</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Signal processing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Tan, T.C</au><au>Bi, Guoan</au><au>Zeng, Yonghong</au><au>Tan, H.N</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>DCT hardware structure for sequentially presented data</atitle><jtitle>Signal processing</jtitle><date>2001-11-01</date><risdate>2001</risdate><volume>81</volume><issue>11</issue><spage>2333</spage><epage>2342</epage><pages>2333-2342</pages><issn>0165-1684</issn><eissn>1872-7557</eissn><coden>SPRODR</coden><abstract>This paper shows that a fast DCT algorithm is mapped into a hardware structure that consists of log 2 N modules. Such a hardware structure can be used for bit-serial word-serial or word-serial bit-parallel implementation. Compared to other methods of hardware implementation, the proposed one provides a naturally interface with sequentially presented input data, achieves a high utilization of hardware, requires a low processing latency and has a modular architecture that can be extended to support different transform sizes.</abstract><cop>Amsterdam</cop><pub>Elsevier B.V</pub><doi>10.1016/S0165-1684(01)00113-X</doi><tpages>10</tpages></addata></record>
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source ScienceDirect Freedom Collection 2022-2024
subjects Applied sciences
Bit-serial processing
Detection, estimation, filtering, equalization, prediction
Discrete cosine transform
Exact sciences and technology
Information, signal and communications theory
Signal and communications theory
Signal, noise
Telecommunications and information theory
title DCT hardware structure for sequentially presented data
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-29T16%3A53%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=DCT%20hardware%20structure%20for%20sequentially%20presented%20data&rft.jtitle=Signal%20processing&rft.au=Tan,%20T.C&rft.date=2001-11-01&rft.volume=81&rft.issue=11&rft.spage=2333&rft.epage=2342&rft.pages=2333-2342&rft.issn=0165-1684&rft.eissn=1872-7557&rft.coden=SPRODR&rft_id=info:doi/10.1016/S0165-1684(01)00113-X&rft_dat=%3Cproquest_cross%3E26685260%3C/proquest_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c368t-44d80b653c11433e1f73ddd21df38102e33a26a20ae5a909ca8ed474820d25713%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=26685260&rft_id=info:pmid/&rfr_iscdi=true