Fault simulation for VHDL based test bench and BIST evaluation

A VHDL based Fault simulation procedure for test bench and test hardware evaluation has been developed. This work is aimed to utilize features of VHDL for more efficient fault simulation. Information about fault detection can be obtained in this environment using fault simulation method and guidelin...

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Bibliographic Details
Main Authors: Farshbaf, H., Zolfy, M., Mirkhani, S., Navabi, Z.
Format: Conference Proceeding
Language:English
Subjects:
Automatic testing
Built-in self-test
Circuit faults
Circuit simulation
Circuit synthesis
Circuit testing
Computational modeling
Fault detection
Hardware
System testing
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Description
Summary:A VHDL based Fault simulation procedure for test bench and test hardware evaluation has been developed. This work is aimed to utilize features of VHDL for more efficient fault simulation. Information about fault detection can be obtained in this environment using fault simulation method and guidelines presented in this report. This environment consists of automated steps, which will lead to fault simulation. Information such as fault coverage, efficiency of test patterns and capability of test hardware to detect faults, can be extracted. Using this environment, one can evaluate test benches and order test vectors or configure BIST (Built-In Self Test) architectures.
ISSN:1081-7735
2377-5386
DOI:10.1109/ATS.2001.990316