A high speed Viterbi decoder using path limited PRML method and its application to 1/2 inch HD full bit rate digital VCR

A new algorithm called path limited PRML is described, which has been used to implement a high speed Viterbi decoder LSI. This LSI has been used to realize an experimental 1/2" DVCR at 1.3 Gbps.

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Bibliographic Details
Published in:IEEE transactions on consumer electronics 2001-02, Vol.47 (1), p.80-86
Main Authors: Hara, M., Yoshinaka, T., Sugizaki, Y., Ohura, S.
Format: Article
Language:English
Subjects:
Algorithms
Bit rate
Circuits
Digital
Digital magnetic recording
Electronics
High definition video
High speed
Large scale integration
Maximum likelihood decoding
Maximum likelihood detection
Parallel processing
Viterbi algorithm
Viterbi decoders
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Description
Summary:A new algorithm called path limited PRML is described, which has been used to implement a high speed Viterbi decoder LSI. This LSI has been used to realize an experimental 1/2" DVCR at 1.3 Gbps.
ISSN:0098-3063
1558-4127
DOI:10.1109/30.920423