An educational tool for testing caches on symmetric multiprocessors

In this article, we present a simulator for cache memory systems on symmetric multiprocessors. This simulator is called SMPCache. It has a full graphic and user-friendly interface, and it operates on PC systems with Windows. The simulator has been conceived as a tool for the teaching of cache memori...

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Bibliographic Details
Published in:Microprocessors and microsystems 2001-06, Vol.25 (4), p.187-194
Main Authors: Vega Rodriguez, M A, Sanchez Perez |h J. M., Gomez Pulido |h J. A.
Format: Article
Language:English
Subjects:
Cache memory system
Quality in education
Symmetric multiprocessor
Trace-driven simulator
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Summary:In this article, we present a simulator for cache memory systems on symmetric multiprocessors. This simulator is called SMPCache. It has a full graphic and user-friendly interface, and it operates on PC systems with Windows. The simulator has been conceived as a tool for the teaching of cache memories on multiprocessors systems. This tool is very useful to evaluate and understand different design alternatives: the number of processors, the cache coherence protocols, schemes for bus arbitration, mapping, replacement policies, cache size, memory block size, etc. Our experiences in the last three years have demonstrated to us the benefits of the simulator for teaching purposes.
ISSN:0141-9331
1872-9436
DOI:10.1016/S0141-9331(01)00111-9