Case study in RSFQ design: fast pipelined parallel adder

• Published in: IEEE transactions on applied superconductivity 1999-06, Vol.9 (2), p.3714-3720
• Main Authors: Bunyk, P., Litskevitch, P.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit properties; Clocks; Computer simulation; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Error analysis; Exact sciences and technology; Fabrication; Fluctuations; Frequency; Gates; Inverters; Josephson junctions; Logic; Logic design; Mathematical models; Pipelines; Polarity; Pulse inverters; Spreads; Timing; VHDL
• ISSN: 1051-8223; 1558-2515
• DOI: 10.1109/77.783835

We present a design for parallel pipelined carry-lookahead Kogge-Stone 32and 64-bit integer adders with the traditional concurrent flow timing scheme, and the results of its gate-level logical simulation using a VHDL model, with parameters reduced from the physical-level simulation of RSFQ cells. The design uses only five different types of bit processing blocks and is easily scalable to any length of the operands. The multi-pulse logic representation together with interchanging logical polarity between pipeline stages is used to simplify the design of the blocks, which contain only two types of clocked RSFQ gates: an inverter and a D-flip-flop. Simulations show that in the absence of thermal fluctuations and random parameter spread the clock frequency of the adder implemented in the projected 0.8 /spl mu/m Nb-trilayer technology could be as high as 150 GHz. However, an approximate account of these factors shows that in order to achieve a 99% adder fabrication yield and a 10/sup -25/ adder error rate the maximal frequency should be reduced to 60 GHz for 1.5% Josephson junction spread and to 52 GHz for 3% spread. Adder latency is close to 260 ps for 32 bits and 320 ps for 64 bits. We plan to re-design the adders to increase their speed.