Dielectric deposition process for Cu/SiO sub 2 integration in a dual damascene interconnection architecture

• Published in: Microelectronic engineering 1999-03, Vol.50 (1-4), p.487-493
• Main Authors: Motte, P, Torres, J, Palleau, J, Tardif, F, Demolliens, O, Bernard, H
• Format: Article
• Language: English
• ISSN: 0167-9317

A challenge to integrate Cu in device interconnections is to avoid Cu diffusion into silicon active zone that could seriously damage device performance, and into interlevel dielectric that could induce shorts or degrade dielectric performance. This paper relates the integration of Cu-CVD with SiO sub 2 . Structures studied are SiO sub 2 , deposited on Cu-CVD, and SiO sub 2 /SiN/Cu structure: a thin SiN layer is deposited on Cu before SiO sub 2 to act as diffusion barrier and as an etch stop during the interconnect structure patterning. Both SiO sub 2 and SiN dielectric processes are made in plasma-enhanced chemical vapor deposition processes, from SiH sub 4 precursor with addition of, respectively, N sub 2 O or NH sub 3 . Cu contamination is shown to occur during the dielectric deposition onto Cu, and is enhanced by the fluorine presence in the deposition chamber. Deposition processes were evaluated in order to lower Cu contamination in the dielectric bulk. On an other hand, a noticeable degradation in Cu layer resistance was evidenced after dielectric deposition due to copper contamination during the dielectric deposition process. This issue can be addressed by the optimization of the dielectric deposition process.