Architecture of a fast Internet switch on chip

This paper presents the use of system-on-chip (SoC) technology for wide-area switching networks and proposes a switching architecture specifically designed for SoC. SoC is particularly useful for switching networks since the interconnection lengths are minimized when a partial or entire network is l...

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Bibliographic Details
Published in:Canadian journal of electrical and computer engineering 2001-07, Vol.26 (3/4), p.147-151
Main Author: Mir, Nader F
Format: Article
Language:English
Subjects:
Broadband
Digital signal processors
Electronic circuits
Electronic switching systems
Integrated circuits
Online Access:Get full text
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Description
Summary:This paper presents the use of system-on-chip (SoC) technology for wide-area switching networks and proposes a switching architecture specifically designed for SoC. SoC is particularly useful for switching networks since the interconnection lengths are minimized when a partial or entire network is laid out on a single chip. A defect-tolerant multipath buffered crossbar with an expandable structure that can easily be scaled up or down according to the choice of chip size is proposed. The architecture is evaluated from different standpoints such as performance, defect tolerance, delay, testability, complexity, yield, and area.
ISSN:0840-8688