Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification

More and more system-on-chip designs require the integration of analog circuits on large digital chips and therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on the analog circuits, information is needed about digital substrate noise generation. A methodolog...

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Bibliographic Details
Main Authors: Van Heijningen, M., Badaroglu, M., Donnay, S., De Man, H., Gielen, G., Engels, M., Bolsens, I.
Format: Conference Proceeding
Language:English
Subjects:
Analog circuits
Circuit noise
Circuit simulation
Coupling circuits
Digital systems
Noise generators
Noise measurement
Semiconductor device modeling
System-on-a-chip
Time domain analysis
Online Access:Request full text
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Summary:More and more system-on-chip designs require the integration of analog circuits on large digital chips and therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on the analog circuits, information is needed about digital substrate noise generation. A methodology for modelling and simulating the time-domain waveform of the generated substrate noise of large digital circuits is verified with measurements on an 86k-gate CMOS ASIC. The difference between simulated and measured substrate noise RMS voltage is
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2001.912665