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High resolution ADC using phase modulation-demodulation architecture
We report successful demonstration of a fully operational integrated superconducting ADC system based on a phase modulation/demodulation architecture. It consists of a high-resolution ADC chip with a multiple-channel race arbiter and integrated bit-pipelined decimation filter, an interface electroni...
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Published in: | IEEE transactions on applied superconductivity 1999-06, Vol.9 (2), p.3016-3019 |
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Main Authors: | , , , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | We report successful demonstration of a fully operational integrated superconducting ADC system based on a phase modulation/demodulation architecture. It consists of a high-resolution ADC chip with a multiple-channel race arbiter and integrated bit-pipelined decimation filter, an interface electronics block converting the ADC output to standard ECL form at sampling rates up to 200 MHz, and a computerized test station performing data acquisition, processing and display in real time. We have demonstrated a fully functional 14-bit ADC chip with 2-channel race arbiter and 16-bit decimation filter with 1:64 decimation ratio operating at 11.2 GS/s. By using additional decimation filtering of the ADC output at room temperature we demonstrated its dynamic programmability and resolution-bandwidth tradeoff. The measured ADC performance (on effective bits) was competitive with the best semiconductor high-resolution ADCs. |
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ISSN: | 1051-8223 1558-2515 |
DOI: | 10.1109/77.783664 |