A 0.25 mu m 3.0 V 1T1C 32 Mb nonvolatile ferroelectric RAM with address transition detector (ATD) and current forcing latch sense amplifier (CFLSA) scheme

A 0.25 mu m 3.0V 1T1C 32Mb nonvolatile ferroelectric RAM with address transition detector (ATD) and current forcing latch sense amplifier (CFLSA) scheme was presented. A nonvolatile 32Mb ferroelectric random-access memory with 0.25 mu m design rules uses ATD control for SRAM applications and a commo...

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Published in:Digest of technical papers - IEEE International Solid-State Circuits Conference 2002-01, p.124-125+430-431
Main Authors: Choi, Mun-Kyu, Jeon, Byung-Gil, Jang, Nakwon, Min, Byung-Jun, Song, Yoon-Jong, Lee, Sung-Yung, Kim, Hyun-Ho, Jung, Dong-Jin, Joo, Heung-Jin, Kim, Kinam
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container_title Digest of technical papers - IEEE International Solid-State Circuits Conference
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creator Choi, Mun-Kyu
Jeon, Byung-Gil
Jang, Nakwon
Min, Byung-Jun
Song, Yoon-Jong
Lee, Sung-Yung
Kim, Hyun-Ho
Jung, Dong-Jin
Joo, Heung-Jin
Kim, Kinam
description A 0.25 mu m 3.0V 1T1C 32Mb nonvolatile ferroelectric RAM with address transition detector (ATD) and current forcing latch sense amplifier (CFLSA) scheme was presented. A nonvolatile 32Mb ferroelectric random-access memory with 0.25 mu m design rules uses ATD control for SRAM applications and a common-plate folded bit-line cell scheme with current forcing latched sense amplifier for low noise level without cell area penalty. It is found that CFLSA enhances sensing margin and noise immunity and reduces chip size by 10.87%.
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title A 0.25 mu m 3.0 V 1T1C 32 Mb nonvolatile ferroelectric RAM with address transition detector (ATD) and current forcing latch sense amplifier (CFLSA) scheme
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