Loading…

A 3 V Delta capital sigma receiver with sampling rate enhancement for CDMA baseband processor IC

The architecture of a three V delta sigma receiver with sampling rate enhancement for CDMA baseband processor integrated circuit (IC) was discussed. The receiver architecture included a first order anti-alias filter, a delta sigma modulator and a comb filter that decimated the output to 9.8304MSampl...

Full description

Saved in:
Bibliographic Details
Published in:Digest of technical papers - IEEE International Solid-State Circuits Conference 2002-01, p.180-181+461
Main Authors: Liu, Ed, Chert, Min, Pan, Mingde
Format: Article
Language:English
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The architecture of a three V delta sigma receiver with sampling rate enhancement for CDMA baseband processor integrated circuit (IC) was discussed. The receiver architecture included a first order anti-alias filter, a delta sigma modulator and a comb filter that decimated the output to 9.8304MSample/s. The results showed that with more than four effective number of bits, the receiver performance was sufficient for CDMA demodulation.
ISSN:0193-6530