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A 3 V Delta capital sigma receiver with sampling rate enhancement for CDMA baseband processor IC
The architecture of a three V delta sigma receiver with sampling rate enhancement for CDMA baseband processor integrated circuit (IC) was discussed. The receiver architecture included a first order anti-alias filter, a delta sigma modulator and a comb filter that decimated the output to 9.8304MSampl...
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Published in: | Digest of technical papers - IEEE International Solid-State Circuits Conference 2002-01, p.180-181+461 |
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Main Authors: | , , |
Format: | Article |
Language: | English |
Online Access: | Get full text |
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Summary: | The architecture of a three V delta sigma receiver with sampling rate enhancement for CDMA baseband processor integrated circuit (IC) was discussed. The receiver architecture included a first order anti-alias filter, a delta sigma modulator and a comb filter that decimated the output to 9.8304MSample/s. The results showed that with more than four effective number of bits, the receiver performance was sufficient for CDMA demodulation. |
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ISSN: | 0193-6530 |